The present invention relates generally to supply of power to integrated circuits, and more particularly to detecting and/or compensating for power supply droops to integrated circuits.
Integrated circuits may be largely quiescent at times, drawing little power, while at other times may in whole or in part require large amounts of power. The changes in utilized power may present difficulties in providing stable power to the circuitry, and voltage supplied may decrease, or droop, when power regulation circuits are faced with rapid increases in power demands. These voltage droops may result in slower operation of integrated circuitry, and may result in combinatorial logic failures, particularly for system on chip (SoC) devices, in which voltage droops may not be uniform over the device.
FIGS. 10A and 10B illustrate a load current transient, in which load current rapidly increases, and a corresponding voltage droop. In the example of FIGS. 10A and 10B, timing failures for combinatorial logic may occur once the supply voltage decreases below 0.9 Volts, which is shown as occurring. In other words, temporary mismatch between load current and voltage regulator current delivery leads to power supply droop.
The effect of supply droops in SoC is to lead to failure in sampled combinational paths. Supply droops increase the delay in logic paths. Supply droops are mainly caused by fast SoC load current transients.